Source/Drain Junction Partition in MOS Snapback Modeling for ESD Simulation
ggNMOS (grounded-gated NMOS)
A novel latch-up free SCR-LDMOS with high holding voltage for a power-rail ESD clamp
Technical considerations and protection mechanism for ESD event...
Modeling MOS snapback and parasitic bipolar action for circuit-level ESD and high current simulations | Semantic Scholar
The dangers of deep snap-back ESD circuit-protection diodes - Analog - Technical articles - TI E2E support forums
TLP measurement of ESD Protection Devices - iST-Integrated Service Technology - TLP measurement of ESD Protection Devices
Time to say farewell to the snapback ggNMOS for ESD protection – SOFICS – Solutions for ICs
Mix‐mode forward‐biased diode with low clamping voltage for robust ESD applications - Qi - 2020 - Electronics Letters - Wiley Online Library
What does good ESD protection look like? | Efficiency Wins
Double Snapback Characteristics in High-Voltage nMOSFETs and the Impact to On-Chip ESD Protection Design
Time to say farewell to the snapback ggNMOS for ESD protection – SOFICS – Solutions for ICs
ON Semiconductor Is Now
Measurement on Snapback Holding Voltage of High-Voltage LDMOS for Latch-Up Consideration
Snapback behavior determines ESD protection effectiveness - SemiWiki
ESD Device Modeling: Part 1 - In Compliance Magazine
Context-Aware SPICE Simulation Improves The Fidelity Of ESD Analysis
Technical considerations and protection mechanism for ESD event...
Measured IV-curve and simplified model for ESD-protection elements with... | Download Scientific Diagram
Impact from IC On-Chip Protection Design on EOS - In Compliance Magazine
Snapback TVS Diode – Unictron
New subcircuit for ESD snapback simulation | Download Scientific Diagram
Are You Paying Proper Attention To Your ESD Design Windows?
Time to say farewell to the snapback ggNMOS for ESD protection – SOFICS – Solutions for ICs
Matching ESD protection to process geometry - Electronic Products
ESD, EMC and PCB recommendations
